Semiconductors are manufactured from small blocks of semi-conductive material containing integrated electrical circuits. The semi-conductive material may be attached to a wafer of electronic-grade silicon (EGS). The combination of semi-conductive material and a wafer is called a “die.” The die may be connected to other electronic components to form part of a larger electronic circuit. These large electronic circuits have been implemented in a variety of technology areas including, but not limited to aerospace and communication systems. Moreover, complex electronic circuits have been used in satellite applications. In these applications it is desirable to have electronic components that are capable of functioning in severe conditions and providing a high level of performance, reliability and density.
These technology systems, however, have limited space for electronic packaging. One known method of creating complex electronic systems having smaller electronic packaging is called “Bare” die stacking. Bare die stacking is where two or more dies are stacked one on top of another to create a multi-chip module. Stacking two or more dies in an integrated circuit allows the circuit to be more complex than a circuit containing a single die. Moreover, die stacking requires less electronic packaging than two dies placed next to one another.
Multi-chip electronic modules, however, are typically limited to three or four dies in a stack. Many of these electronic modules are manufactured using “standoff” interposers. These interposers are placed between the bare die and wire bonds to provide electrical connections. As the stacks of the bare die becomes progressively higher additional courses of wire bonding must be escaped from the stack. This approach not only becomes more and more unwieldy as additional die are stacked but also requires more space on the next higher level of packaging as the wires are connected. Moreover, the additional courses of wire bonding may also reduce device performance in high-speed electronic applications. The practical limit for stacking devices in this fashion is four high per packaging surface.
Stacking two or more dies together, however, increases the risk that the integrated circuit will not function. Dies cannot be fully tested prior to creating the multi-chip electronic module. Only when the electronic module is fully assembled can the dies be fully tested. If one die in the electronic module is defective, then the entire module is defective. Therefore, bare die stacking allows for creating complex electronic circuits having smaller electronic packaging, but this method increases the risk that the final multi-chip electronic module will not function.
A need, therefore, exists for a multi-chip electronic module having improved electronic circuit density without adversely affecting the circuit reliability.